Power distribution paths in 3-D ICs

Vasilis F. Pavlidis, Giovanni De Micheli

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


    Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (TSVs) in most of the manufacturing techniques for three-dimensional (3-D) circuits. As shown in this paper, these vertical interconnects provide additional low impedance paths for distributing power and ground within a 3-D circuit. These paths, however, have not been considered in the design process of 3-D power and ground distribution networks. By exploiting these additional paths, the IR drop within each plane is reduced. Alternatively, the routing congestion caused by the TSVs can be decreased by removing stacks of metal vias that are used within a power distribution network. Additionally, the required decoupling capacitance for a circuit can be reduced, resulting in significant savings in area. Case studies of power grids demonstrate a significant reduction of 22% in the number of intraplane vias. Alternatively, a 25% decrease in the decoupling capacitance can be achieved. © 2009 ACM.
    Original languageEnglish
    Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|Proc. ACM Great Lakes Symp. VLSI GLSVLSI
    Place of PublicationNew York, USA
    PublisherAssociation for Computing Machinery
    Number of pages5
    ISBN (Print)9781605585222
    Publication statusPublished - 2009
    Event19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 - Boston, MA
    Duration: 1 Jul 2009 → …


    Conference19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09
    CityBoston, MA
    Period1/07/09 → …


    • 3-D ICs
    • 3-D integration
    • Power distribution network
    • Through silicon vias


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