Power management in the amulet microprocessors

Steve B. Furber; Aristides Efthymiou; Jim D. Garside; David W. Lloyd; Mike J G Lewis; Steve Temple

doi:10.1109/54.914617

Power management in the amulet microprocessors

Steve B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J G Lewis, Steve Temple

Advanced Processor Technology

Research output: Contribution to journal › Article › peer-review

Abstract

Amulet microprocessors are asynchronous (clockless) implementations of the ARM 32-bit RISC architecture. Their asynchronous control framework has positive benefits for low-power applications because it reduces activity to the minimum required to perform a task, whereas a clock inevitably incurs wasteful activity. © 2001 IEEE.

Original language	English
Pages (from-to)	42-51
Number of pages	9
Journal	IEEE Design and Test of Computers
Volume	18
Issue number	2
DOIs	https://doi.org/10.1109/54.914617
Publication status	Published - Mar 2001

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@article{11a2b2c9e6484a4c8396fe0b9edb5d5f,

title = "Power management in the amulet microprocessors",

abstract = "Amulet microprocessors are asynchronous (clockless) implementations of the ARM 32-bit RISC architecture. Their asynchronous control framework has positive benefits for low-power applications because it reduces activity to the minimum required to perform a task, whereas a clock inevitably incurs wasteful activity. {\textcopyright} 2001 IEEE.",

author = "Furber, {Steve B.} and Aristides Efthymiou and Garside, {Jim D.} and Lloyd, {David W.} and Lewis, {Mike J G} and Steve Temple",

year = "2001",

month = mar,

doi = "10.1109/54.914617",

language = "English",

volume = "18",

pages = "42--51",

journal = "IEEE Design and Test of Computers",

publisher = "IEEE Computer Society ",

number = "2",

}

TY - JOUR

T1 - Power management in the amulet microprocessors

AU - Furber, Steve B.

AU - Efthymiou, Aristides

AU - Garside, Jim D.

AU - Lloyd, David W.

AU - Lewis, Mike J G

AU - Temple, Steve

PY - 2001/3

Y1 - 2001/3

N2 - Amulet microprocessors are asynchronous (clockless) implementations of the ARM 32-bit RISC architecture. Their asynchronous control framework has positive benefits for low-power applications because it reduces activity to the minimum required to perform a task, whereas a clock inevitably incurs wasteful activity. © 2001 IEEE.

AB - Amulet microprocessors are asynchronous (clockless) implementations of the ARM 32-bit RISC architecture. Their asynchronous control framework has positive benefits for low-power applications because it reduces activity to the minimum required to perform a task, whereas a clock inevitably incurs wasteful activity. © 2001 IEEE.

U2 - 10.1109/54.914617

DO - 10.1109/54.914617

M3 - Article

VL - 18

SP - 42

EP - 51

JO - IEEE Design and Test of Computers

JF - IEEE Design and Test of Computers

IS - 2

ER -

Power management in the amulet microprocessors

Abstract

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