TY - GEN
T1 - Powerhammering through Glitch Amplification – Attacks and Mitigation
AU - Mätas, Kaspar
AU - La, Tuan
AU - Pham, Khoa
AU - Koch, Dirk
N1 - Funding Information:
ACKNOWLEDGMENT This work is kindly supported by the UK National Cy-ber Security Centre through the project rFAS (grant agreement 4212204/RFA 15971) and by the European Commission through the project EuroEXA (grants 754337). We also thank the Xilinx University Program for providing tools and boards.
Publisher Copyright:
© 2020 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/5/1
Y1 - 2020/5/1
N2 - Recent work on FPGA hardware security showed a substantial potential risk through power-hammering, which uses high switching activity in order to create excessive dynamic power loads. Virtually all present power-hammering attack scenarios are based on some kind of ring oscillators for which mitigation strategies exist. In this paper, we use a different strategy to create excessive dynamic power consumption: glitch amplification. By carefully designing XOR trees, fast switching wires can be implemented that, while driving high fan-out nets, can draw enough power to crash an FPGA. In addition to the attack (which is crashing an Ultra96 board), we will present a scanner for detecting malicious glitch amplifying FPGA designs.
AB - Recent work on FPGA hardware security showed a substantial potential risk through power-hammering, which uses high switching activity in order to create excessive dynamic power loads. Virtually all present power-hammering attack scenarios are based on some kind of ring oscillators for which mitigation strategies exist. In this paper, we use a different strategy to create excessive dynamic power consumption: glitch amplification. By carefully designing XOR trees, fast switching wires can be implemented that, while driving high fan-out nets, can draw enough power to crash an FPGA. In addition to the attack (which is crashing an Ultra96 board), we will present a scanner for detecting malicious glitch amplifying FPGA designs.
U2 - 10.1109/FCCM48280.2020.00018
DO - 10.1109/FCCM48280.2020.00018
M3 - Conference contribution
SN - 9781728158037
T3 - Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020
SP - 65
EP - 69
BT - Proceedings - 28th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020
ER -