Prime indicants: A synthesis method for indicating combinational logic blocks

W. B. Toms; D. A. Edwards

doi:10.1109/ASYNC.2009.24

Prime indicants: A synthesis method for indicating combinational logic blocks

W. B. Toms, D. A. Edwards

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs of a function block. Covers are constructed by determining the minimal cost set of Prime Indicants which are required to indicate all of the input transitions of the function block. The results of the procedure are demonstrated on a wide range of combinational logic blocks and show a reduction in literal count of between 38-99%. © 2009 IEEE.

Original language	English
Title of host publication	Proceedings - International Symposium on Asynchronous Circuits and Systems\|Proc. Int. Symp. Asynchr. Circuits Syst.
Place of Publication	USA
Publisher	IEE
Pages	139-150
Number of pages	11
ISBN (Print)	9780769536163
DOIs	https://doi.org/10.1109/ASYNC.2009.24
Publication status	Published - 2009
Event	15th International Symposium on Asynchronous Circuits and Systems, ASYNC 2009 - Chapel Hill, NC Duration: 1 Jul 2009 → …

Conference

Conference	15th International Symposium on Asynchronous Circuits and Systems, ASYNC 2009
City	Chapel Hill, NC
Period	1/07/09 → …

Keywords

combinational circuits , network synthesis

Access to Document

10.1109/ASYNC.2009.24

Cite this

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title = "Prime indicants: A synthesis method for indicating combinational logic blocks",

abstract = "Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs of a function block. Covers are constructed by determining the minimal cost set of Prime Indicants which are required to indicate all of the input transitions of the function block. The results of the procedure are demonstrated on a wide range of combinational logic blocks and show a reduction in literal count of between 38-99%. {\textcopyright} 2009 IEEE.",

keywords = "combinational circuits , network synthesis",

author = "Toms, {W. B.} and Edwards, {D. A.}",

year = "2009",

doi = "10.1109/ASYNC.2009.24",

language = "English",

isbn = "9780769536163",

pages = "139--150",

booktitle = "Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.",

publisher = "IEE",

address = "United Kingdom",

note = "15th International Symposium on Asynchronous Circuits and Systems, ASYNC 2009 ; Conference date: 01-07-2009",

}

Toms, WB & Edwards, DA 2009, Prime indicants: A synthesis method for indicating combinational logic blocks. in Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.. IEE, USA, pp. 139-150, 15th International Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, 1/07/09. https://doi.org/10.1109/ASYNC.2009.24

TY - GEN

T1 - Prime indicants: A synthesis method for indicating combinational logic blocks

AU - Toms, W. B.

AU - Edwards, D. A.

PY - 2009

Y1 - 2009

N2 - Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs of a function block. Covers are constructed by determining the minimal cost set of Prime Indicants which are required to indicate all of the input transitions of the function block. The results of the procedure are demonstrated on a wide range of combinational logic blocks and show a reduction in literal count of between 38-99%. © 2009 IEEE.

AB - Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outputs of a function block. Covers are constructed by determining the minimal cost set of Prime Indicants which are required to indicate all of the input transitions of the function block. The results of the procedure are demonstrated on a wide range of combinational logic blocks and show a reduction in literal count of between 38-99%. © 2009 IEEE.

KW - combinational circuits , network synthesis

U2 - 10.1109/ASYNC.2009.24

DO - 10.1109/ASYNC.2009.24

M3 - Conference contribution

SN - 9780769536163

SP - 139

EP - 150

BT - Proceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.

PB - IEE

CY - USA

T2 - 15th International Symposium on Asynchronous Circuits and Systems, ASYNC 2009

Y2 - 1 July 2009

ER -

Prime indicants: A synthesis method for indicating combinational logic blocks

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