Prospects for Low-power Acceleration of HPC Workloads in EuroExa: FPGA Acceleration of a Numerical Weather Forecast Code

The EuroExa project proposes a High-Performance Computing (HPC) architecture which is both scalable to Exascale performance levels and delivers world-leading power efficiency. This is achieved through the use of low-power ARM processors accelerated by closely-coupled FPGA programmable components. In order to demonstrate the efficacy of the design, the EuroExa project includes application porting work across a rich set of applications. One such application is the new weather and climate model, LFRic (named in honour of Lewis Fry Richardson), which is being developed by the UK Met Office and its partners for operational deployment in the middle of the next decade. Much of the run-time of the LFRic model consists of compute intensive operations which are suitable for acceleration using FPGAs. We have selected the Xilinx Vivado toolset including High-Level Synthesis (HLS) which generates IP blocks that can be combined with other standard IP blocks in Vivado Design Studio and a bitstream generated for programming the FPGA. A design using twelve matrix-vector IP blocks achieves 5.34 double precision Gflop/s. We shall discuss the implementation, the performance achieved and the prospects for acceleration of the full LFRic weather model.