Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes

Asynchronous circuit design is a promising technology for large-scale multi-core systems. As a family of asynchronous circuits, Quasi-delay-insensitive (QDI) circuits have been widely used to build chip-level long interconnects due to their tolerance to delay variations. However, \{QDI\} interconnects are vulnerable to faults. Traditional fault-tolerant techniques for synchronous circuits cannot be easily used to protect \{QDI\} interconnects. This paper focuses on protecting \{QDI\} interconnects from transient faults. The first contribution of this paper is a fault-tolerant delay-insensitive redundant check code named DIRC. Using \{DIRC\} in 4-phase 1-of-n \{QDI\} pipelines, all 1-bit and some multi-bit transient faults are tolerated. The \{DIRC\} and basic pipeline stages are mutually exchangeable. Arbitrary basic stages can be replaced by \{DIRC\} ones to strengthen fault-tolerance. This feature permits designers to use \{DIRC\} flexibly according to the practical design requirement. The second contribution is a redundant technique protecting the acknowledge wires (RPA). Experimental results indicate that \{DIRC\} pipelines have moderate area and speed overheads. Compared with unprotected basic pipelines, the average speed decrease of \{DIRC\} pipelines is less than 50%, with the 128-bit 1-of-2 \{DIRC\} pipeline only 28% slower. In severe environments with multi-bit transient faults, the fault-tolerance capability of \{DIRC\} pipelines increases thousands-fold.