Reducing code size in scheduling synchronous dataflow graphs on multicore systems

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A Synchronous Dataflow Graph (SDFG) is a widely used abstraction to capture the characteristics of a number of applications often running on embedded systems. When scheduling/mapping an SDFG on a multicore embedded system, the code of tasks may have to be duplicated onto multiple cores to fully utilize the parallelism of the multicore system. However, such an approach may increase the overall code size in the system, which may not be desirable. This paper proposes a code-size-aware scheduling heuristic, which decreases code duplication of SDFGs on multicore systems, hence minimizing overall code size while not affecting throughput. In experiments, the proposed heuristic achieves significant code size reduction for all the tested SDFGs compared with a state-of-art recently proposed scheduling algorithm.

Original languageEnglish
Title of host publicationPARMA-DITAM 2018 - Proceedings
Subtitle of host publication9th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms
PublisherAssociation for Computing Machinery
Pages57-62
Number of pages6
ISBN (Electronic)9781450364447
DOIs
Publication statusPublished - 23 Jan 2018
Event9th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2018 - Manchester, United Kingdom
Duration: 23 Jan 2018 → …

Conference

Conference9th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2018
Country/TerritoryUnited Kingdom
CityManchester
Period23/01/18 → …

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