Register locking in an asynchronous microprocessor

N.C. Paver; P. Day; S.B. Furber; J.D. Garside; J.V. Woods

doi:10.1109/ICCD.1992.276287

Register locking in an asynchronous microprocessor

N.C. Paver, P. Day, S.B. Furber, J.D. Garside, J.V. Woods

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

A high-performance register bank is a central component of a RISC processor. A novel register bank design has been developed, as an integral part of a self-timed implementation of a commercial RISC microprocessor, to address the problem of register interlocking in an asynchronous micropipelined execution unit. The problem in an asynchronous design is to maintain coherent register operation while allowing concurrent read and write accesses with arbitrary timing. The solution presented here includes a novel arbiter-free locking mechanism which enables efficient read operations in the presence of multiple pending write operations.

Original language	English
Title of host publication	Proceedings 1992 IEEE International Conference on Computer Design:
Subtitle of host publication	VLSI in Computers & Processors
Place of Publication	Cambridge, MA
Publisher	IEEE
Pages	351-355
Number of pages	5
ISBN (Print)	0818631104
DOIs	https://doi.org/10.1109/ICCD.1992.276287
Publication status	Published - 15 Oct 1992
Event	IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, United States Duration: 11 Oct 1992 → 14 Oct 1992 https://ieeexplore.ieee.org/xpl/conhome/442/proceeding

Conference

Conference	IEEE International Conference on Computer Design
Abbreviated title	ICCD
Country/Territory	United States
City	Cambridge, MA
Period	11/10/92 → 14/10/92
Internet address	https://ieeexplore.ieee.org/xpl/conhome/442/proceeding

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10.1109/ICCD.1992.276287

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@inproceedings{85c9e1559ce34fd89bd890f11a71f673,

title = "Register locking in an asynchronous microprocessor",

abstract = "A high-performance register bank is a central component of a RISC processor. A novel register bank design has been developed, as an integral part of a self-timed implementation of a commercial RISC microprocessor, to address the problem of register interlocking in an asynchronous micropipelined execution unit. The problem in an asynchronous design is to maintain coherent register operation while allowing concurrent read and write accesses with arbitrary timing. The solution presented here includes a novel arbiter-free locking mechanism which enables efficient read operations in the presence of multiple pending write operations.",

author = "N.C. Paver and P. Day and S.B. Furber and J.D. Garside and J.V. Woods",

year = "1992",

month = oct,

day = "15",

doi = "10.1109/ICCD.1992.276287",

language = "English",

isbn = "0818631104",

pages = "351--355",

booktitle = "Proceedings 1992 IEEE International Conference on Computer Design:",

publisher = "IEEE",

address = "United States",

note = "IEEE International Conference on Computer Design : VLSI in Computers & Processors, ICCD ; Conference date: 11-10-1992 Through 14-10-1992",

url = "https://ieeexplore.ieee.org/xpl/conhome/442/proceeding",

}

Paver, NC, Day, P, Furber, SB, Garside, JD & Woods, JV 1992, Register locking in an asynchronous microprocessor. in Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors. IEEE, Cambridge, MA, pp. 351-355, IEEE International Conference on Computer Design, Cambridge, MA, United States, 11/10/92. https://doi.org/10.1109/ICCD.1992.276287

TY - GEN

T1 - Register locking in an asynchronous microprocessor

AU - Paver, N.C.

AU - Day, P.

AU - Furber, S.B.

AU - Garside, J.D.

AU - Woods, J.V.

PY - 1992/10/15

Y1 - 1992/10/15

N2 - A high-performance register bank is a central component of a RISC processor. A novel register bank design has been developed, as an integral part of a self-timed implementation of a commercial RISC microprocessor, to address the problem of register interlocking in an asynchronous micropipelined execution unit. The problem in an asynchronous design is to maintain coherent register operation while allowing concurrent read and write accesses with arbitrary timing. The solution presented here includes a novel arbiter-free locking mechanism which enables efficient read operations in the presence of multiple pending write operations.

AB - A high-performance register bank is a central component of a RISC processor. A novel register bank design has been developed, as an integral part of a self-timed implementation of a commercial RISC microprocessor, to address the problem of register interlocking in an asynchronous micropipelined execution unit. The problem in an asynchronous design is to maintain coherent register operation while allowing concurrent read and write accesses with arbitrary timing. The solution presented here includes a novel arbiter-free locking mechanism which enables efficient read operations in the presence of multiple pending write operations.

U2 - 10.1109/ICCD.1992.276287

DO - 10.1109/ICCD.1992.276287

M3 - Conference contribution

SN - 0818631104

SP - 351

EP - 355

BT - Proceedings 1992 IEEE International Conference on Computer Design:

PB - IEEE

CY - Cambridge, MA

T2 - IEEE International Conference on Computer Design

Y2 - 11 October 1992 through 14 October 1992

ER -

Register locking in an asynchronous microprocessor

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