Register locking in an asynchronous microprocessor

N.C. Paver, P. Day, S.B. Furber, J.D. Garside, J.V. Woods

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


A high-performance register bank is a central component of a RISC processor. A novel register bank design has been developed, as an integral part of a self-timed implementation of a commercial RISC microprocessor, to address the problem of register interlocking in an asynchronous micropipelined execution unit. The problem in an asynchronous design is to maintain coherent register operation while allowing concurrent read and write accesses with arbitrary timing. The solution presented here includes a novel arbiter-free locking mechanism which enables efficient read operations in the presence of multiple pending write operations.
Original languageEnglish
Title of host publicationProceedings 1992 IEEE International Conference on Computer Design:
Subtitle of host publicationVLSI in Computers & Processors
Place of PublicationCambridge, MA
Number of pages5
ISBN (Print)0818631104
Publication statusPublished - 15 Oct 1992
EventIEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, United States
Duration: 11 Oct 199214 Oct 1992


ConferenceIEEE International Conference on Computer Design
Abbreviated titleICCD
Country/TerritoryUnited States
CityCambridge, MA
Internet address


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