Repeater insertion for two-terminal nets in three-dimensional integrated circuits

Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans. © Institute for Computer Science, Social-Informatics and Telecommunications Engineering 2009.
    Original languageEnglish
    Title of host publicationLecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering|Lect. Notes Inst. Comput. Sci. Soc. Informatics Telecommun. Eng.
    PublisherSpringer Nature
    Pages141-150
    Number of pages9
    Volume20
    ISBN (Print)3642048498, 9783642048494
    DOIs
    Publication statusPublished - 2009
    Event4th International ICST Conference on Nano-Net, Nano-Net 2009 - Lucerne
    Duration: 1 Jul 2009 → …

    Conference

    Conference4th International ICST Conference on Nano-Net, Nano-Net 2009
    CityLucerne
    Period1/07/09 → …

    Keywords

    • 3-D ICs
    • On-chip interconnect
    • Repeater insertion
    • Timing optimization

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