Abstract
Some parallel applications do not require a precise imitation of the behaviour of the physically shared memory programming model. Consequently, certain parallel machine architectures have elected to emphasize different required coherency properties because of possible efficiency gains. This has led to various definitions of models of store coherency. These definitions have not been amenable to detailed analysis and, consequently, inconsistencies have resulted. In this paper a unified framework is proposed in which different models of store coherency are developed systematically by progressively relaxing the constraints that they have to satisfy. A demonstration is given of how formal reasoning can be carried out to compare different models. Some real-life systems are considered and a definition of a version of weak coherency is found to be incomplete.
| Original language | English |
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| Title of host publication | Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing|Proc 5 IEEE Symp Parallel Distrib Proc |
| Editors | Anon |
| Place of Publication | Los Alamitos, CA, United States |
| Publisher | IEEE |
| Pages | 391-398 |
| Number of pages | 7 |
| ISBN (Print) | 081864222X |
| Publication status | Published - 1993 |
| Event | Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing - Dallas, TX, USA Duration: 1 Jul 1993 → … http://dblp.uni-trier.de/db/conf/spdp/spdp1993.html#HussakK93http://dblp.uni-trier.de/rec/bibtex/conf/spdp/HussakK93.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/spdp/HussakK93 |
Conference
| Conference | Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing |
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| City | Dallas, TX, USA |
| Period | 1/07/93 → … |
| Internet address |