Abstract
Integrated circuits (ICs) based on asynchronous logic design are enjoying a resurgence as more and more circuit designers realize the advantages of this design concept over clock designs. Clock circuits waste power by clocking all parts of the chip and must be margined for worst case processes, unlike asynchronous logic ICs which allow optimum hardware concurrency and offers improve electromagnetic compatibility. However, production quality assurance techniques must first be enhanced to address the complexities involved in the testing of such circuits.
| Original language | English |
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| Title of host publication | IEEE International Test Conference (TC) |
| Publisher | IEEE |
| Pages | 938 |
| Number of pages | 1 |
| Publication status | Published - 1996 |
| Event | Proceedings of the 1996 IEEE International Test Conference - Washington, DC, USA Duration: 20 Oct 1996 → 24 Oct 1996 |
Conference
| Conference | Proceedings of the 1996 IEEE International Test Conference |
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| City | Washington, DC, USA |
| Period | 20/10/96 → 24/10/96 |