SCAMP-3: A vision chip with SIMD current-mode analogue processor array

    Research output: Chapter in Book/Report/Conference proceedingChapter


    In this chapter, the architecture, design and implementation of a vision chip with general-purpose programmable pixel-parallel cellular processor array, operating in single instruction multiple data (SIMD) mode is presented. The SIMD concurrent processor architecture is ideally suited to implementing low-level image processing algorithms. The datapath components (registers, I/O, arithmetic unit) of the processing elements of the array are built using switched-current circuits. The combination of a straightforward SIMD programming model, with digital microprocessor-like control and analogue datapath, produces an easy-to-use, flexible system, with high-degree of programmability, and efficient, low-power, small-footprint, circuit implementation. The SCAMP-3 chip integrates 128 ×128 pixel-processors and a flexible read-out circuitry, while the control system is fully digital, and currently implemented off-chip. The device implements low-level image processing algorithms on the focal plane, with a peak performance of more than 20 GOPS, and power consumption below 240mW. © 2011 Springer Science+Business Media, LLC.
    Original languageEnglish
    Title of host publicationFocal-Plane Sensor-Processor Chips|Focal-Pl. Sens.-Process. Chips
    PublisherSpringer Nature
    Number of pages26
    Publication statusPublished - 2011


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