Scan testing of micropipelines

O. A. Petlin, S. B. Furber

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinatorial processing logic and state holding elements can be derived using standard test generation techniques.
Original languageEnglish
Title of host publicationProceedings of the IEEE VLSI Test Symposium|Proc IEEE VLSI Test Symp
PublisherIEEE Computer Society
Number of pages5
Publication statusPublished - 1995
EventProceedings of the 13th IEEE VLSI Test Symposium - Princeton, NJ, USA
Duration: 1 Jul 1995 → …


ConferenceProceedings of the 13th IEEE VLSI Test Symposium
CityPrinceton, NJ, USA
Period1/07/95 → …
Internet address


Dive into the research topics of 'Scan testing of micropipelines'. Together they form a unique fingerprint.

Cite this