Self-timed section-carry based carry lookahead adders and the concept of alias logic

This paper makes two important contributions to the domain of self-timed computer arithmetic. Firstly, a gate-level synthesis of self-timed carry lookahead (CLA) adders based on the notion of section-carry is discussed. Three types of CLA adder architectures have been conceived and both homogeneous and heterogeneous delay-insensitive (DI) data encoding schemes are considered. In general, for higher-order additions, the self-timed CLA adder is found to result in reduced latency than the carry ripple version by 38.6%. However, the latter occupies less area and dissipates less power than the former by 37.8% and 17.4%, respectively. Secondly, a new concept of alias logic is introduced in this work which is useful for delay optimization of iterative circuit specifications - here; this concept is applied to effect latency reduction in self-timed CLA adders. By incorporating alias logic, the propagation delay of the intermediate carries in a CLA structure is further minimized to the tune of 27.2% on average, whilst accompanied by marginal area and power penalties of the order of just 2% and 1.5%, respectively.