Sensitive registers: A technique for reducing the fetch bandwidth in low-power microprocessors

A. Robinson; J. D. Garside

doi:10.1145/1228784.1228820

Sensitive registers: A technique for reducing the fetch bandwidth in low-power microprocessors

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

Reducing power consumption is an increasingly important consideration in a wide variety of systems. One source of inefficiency in a 'general purpose' computing system is the (often repeated) overhead of fetching instructions which are used to direct the algorithm rather than process the data directly. This paper proposes a mechanism for the association of frequently used control information with the processor's registers, removing the need to fetch it repeatedly from the instruction stream. Some results are presented to demonstrate both power savings and speed gains over an existing low-power system and the potential for further savings in other programming models is explored. Copyright 2007 ACM.

Original language	English
Title of host publication	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI\|Proc. ACM Great Lakes Symp. VLSI GLSVLSI
Publisher	Association for Computing Machinery
Pages	138-143
Number of pages	5
ISBN (Print)	159593605X, 9781595936059
DOIs	https://doi.org/10.1145/1228784.1228820
Publication status	Published - 2007
Event	17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore Duration: 1 Jul 2007 → … http://intranet.cs.man.ac.uk/apt/publications/papers/AR_GLVLSI07.php

Conference

Conference	17th Great Lakes Symposium on VLSI, GLSVLSI'07
City	Stresa-Lago Maggiore
Period	1/07/07 → …
Internet address	http://intranet.cs.man.ac.uk/apt/publications/papers/AR_GLVLSI07.php

Keywords

Memory bandwidth
Power efficiency
Processors
Registers

Access to Document

10.1145/1228784.1228820

Cite this

@inproceedings{824216769f634007b3781bfd9e4f6b40,

title = "Sensitive registers: A technique for reducing the fetch bandwidth in low-power microprocessors",

abstract = "Reducing power consumption is an increasingly important consideration in a wide variety of systems. One source of inefficiency in a 'general purpose' computing system is the (often repeated) overhead of fetching instructions which are used to direct the algorithm rather than process the data directly. This paper proposes a mechanism for the association of frequently used control information with the processor's registers, removing the need to fetch it repeatedly from the instruction stream. Some results are presented to demonstrate both power savings and speed gains over an existing low-power system and the potential for further savings in other programming models is explored. Copyright 2007 ACM.",

keywords = "Memory bandwidth, Power efficiency, Processors, Registers",

author = "A. Robinson and Garside, {J. D.}",

year = "2007",

doi = "10.1145/1228784.1228820",

language = "English",

isbn = "159593605X",

pages = "138--143",

booktitle = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|Proc. ACM Great Lakes Symp. VLSI GLSVLSI",

publisher = "Association for Computing Machinery",

address = "United States",

note = "17th Great Lakes Symposium on VLSI, GLSVLSI'07 ; Conference date: 01-07-2007",

url = "http://intranet.cs.man.ac.uk/apt/publications/papers/AR_GLVLSI07.php",

}

Robinson, A & Garside, JD 2007, Sensitive registers: A technique for reducing the fetch bandwidth in low-power microprocessors. in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|Proc. ACM Great Lakes Symp. VLSI GLSVLSI. Association for Computing Machinery, pp. 138-143, 17th Great Lakes Symposium on VLSI, GLSVLSI'07, Stresa-Lago Maggiore, 1/07/07. https://doi.org/10.1145/1228784.1228820

Sensitive registers: A technique for reducing the fetch bandwidth in low-power microprocessors. / Robinson, A.; Garside, J. D.
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|Proc. ACM Great Lakes Symp. VLSI GLSVLSI. Association for Computing Machinery, 2007. p. 138-143.

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Sensitive registers: A technique for reducing the fetch bandwidth in low-power microprocessors

AU - Robinson, A.

AU - Garside, J. D.

PY - 2007

Y1 - 2007

N2 - Reducing power consumption is an increasingly important consideration in a wide variety of systems. One source of inefficiency in a 'general purpose' computing system is the (often repeated) overhead of fetching instructions which are used to direct the algorithm rather than process the data directly. This paper proposes a mechanism for the association of frequently used control information with the processor's registers, removing the need to fetch it repeatedly from the instruction stream. Some results are presented to demonstrate both power savings and speed gains over an existing low-power system and the potential for further savings in other programming models is explored. Copyright 2007 ACM.

AB - Reducing power consumption is an increasingly important consideration in a wide variety of systems. One source of inefficiency in a 'general purpose' computing system is the (often repeated) overhead of fetching instructions which are used to direct the algorithm rather than process the data directly. This paper proposes a mechanism for the association of frequently used control information with the processor's registers, removing the need to fetch it repeatedly from the instruction stream. Some results are presented to demonstrate both power savings and speed gains over an existing low-power system and the potential for further savings in other programming models is explored. Copyright 2007 ACM.

KW - Memory bandwidth

KW - Power efficiency

KW - Processors

KW - Registers

U2 - 10.1145/1228784.1228820

DO - 10.1145/1228784.1228820

M3 - Conference contribution

SN - 159593605X

SN - 9781595936059

SP - 138

EP - 143

BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|Proc. ACM Great Lakes Symp. VLSI GLSVLSI

PB - Association for Computing Machinery

T2 - 17th Great Lakes Symposium on VLSI, GLSVLSI'07

Y2 - 1 July 2007

ER -

Sensitive registers: A technique for reducing the fetch bandwidth in low-power microprocessors

Abstract

Conference

Keywords

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