SpiNNaker: A 1-W 18-core system-on-chip for massively-parallel neural network simulation

Eustace Painkras, Luis A. Plana, Jim Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R. Lester, Andrew D. Brown, Steve B. Furber

Research output: Contribution to journalArticlepeer-review


The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm2 die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements. © 1966-2012 IEEE.
Original languageEnglish
Article number6515159
Pages (from-to)1943-1953
Number of pages10
JournalIEEE Journal of Solid State Circuits
Issue number8
Publication statusPublished - 2013


  • Asynchronous interconnect
  • Chip multiprocessor
  • Energy efficiency
  • Globally asynchronous locally synchronous (GALS)
  • Network-on-chip
  • Neuromorphic hardware
  • Real-time simulation
  • Spiking neural networks (SNNs)


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