SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation

Eustace Painkras, Luis A. Plana, Jim Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David Clark, Cameron Patterson, Steve Furber

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements. © 2012 IEEE.
Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf
PublisherIEEE
ISBN (Print)9781467315555
DOIs
Publication statusPublished - 2012
Event34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA
Duration: 1 Jul 2012 → …

Conference

Conference34th Annual Custom Integrated Circuits Conference, CICC 2012
CitySan Jose, CA
Period1/07/12 → …

Fingerprint

Dive into the research topics of 'SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation'. Together they form a unique fingerprint.

Cite this