SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation

Eustace Painkras; Luis A. Plana; Jim Garside; Steve Temple; Simon Davidson; Jeffrey Pepper; David Clark; Cameron Patterson; Steve Furber

doi:10.1109/CICC.2012.6330636

SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation

Eustace Painkras
, Luis A. Plana
, Jim Garside
, Steve Temple
, Simon Davidson
, Jeffrey Pepper
, David Clark
, Cameron Patterson
, Steve Furber

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements. © 2012 IEEE.

Original language	English
Title of host publication	Proceedings of the Custom Integrated Circuits Conference\|Proc Custom Integr Circuits Conf
Publisher	IEEE
ISBN (Print)	9781467315555
DOIs	https://doi.org/10.1109/CICC.2012.6330636
Publication status	Published - 2012
Event	34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA Duration: 1 Jul 2012 → …

Conference

Conference	34th Annual Custom Integrated Circuits Conference, CICC 2012
City	San Jose, CA
Period	1/07/12 → …

Access to Document

10.1109/CICC.2012.6330636

Cite this

@inproceedings{efd4615b7bb64d9d899c6aacae209fc5,

title = "SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation",

abstract = "The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements. {\textcopyright} 2012 IEEE.",

author = "Eustace Painkras and Plana, \{Luis A.\} and Jim Garside and Steve Temple and Simon Davidson and Jeffrey Pepper and David Clark and Cameron Patterson and Steve Furber",

year = "2012",

doi = "10.1109/CICC.2012.6330636",

language = "English",

isbn = "9781467315555",

booktitle = "Proceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf",

publisher = "IEEE",

address = "United States",

note = "34th Annual Custom Integrated Circuits Conference, CICC 2012 ; Conference date: 01-07-2012",

}

Painkras, E, Plana, LA, Garside, J, Temple, S, Davidson, S, Pepper, J, Clark, D, Patterson, C & Furber, S 2012, SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation. in Proceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf. IEEE, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, 1/07/12. https://doi.org/10.1109/CICC.2012.6330636

TY - GEN

T1 - SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation

AU - Painkras, Eustace

AU - Plana, Luis A.

AU - Garside, Jim

AU - Temple, Steve

AU - Davidson, Simon

AU - Pepper, Jeffrey

AU - Clark, David

AU - Patterson, Cameron

AU - Furber, Steve

PY - 2012

Y1 - 2012

N2 - The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements. © 2012 IEEE.

AB - The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements. © 2012 IEEE.

U2 - 10.1109/CICC.2012.6330636

DO - 10.1109/CICC.2012.6330636

M3 - Conference contribution

SN - 9781467315555

BT - Proceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf

PB - IEEE

T2 - 34th Annual Custom Integrated Circuits Conference, CICC 2012

Y2 - 1 July 2012

ER -

SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation

Abstract

Conference

Access to Document

Fingerprint

Cite this