SpiNNaker: Fault tolerance in a power- and area- Constrained large-Scale neuromimetic architecture

Javier Navaridas; Steve Furber; Jim Garside; Xin Jin; Mukaram Khan; David Lester; Mikel Luján; José Miguel-Alonso; Eustace Painkras; Cameron Patterson; Luis A. Plana; Alexander Rast; Dominic Richards; Yebin Shi; Steve Temple; Jian Wu; Shufan Yang

doi:10.1016/j.parco.2013.09.001

SpiNNaker: Fault tolerance in a power- and area- Constrained large-Scale neuromimetic architecture

Javier Navaridas, Steve Furber, Jim Garside, Xin Jin, Mukaram Khan, David Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang

Advanced Processor Technology

Research output: Contribution to journal › Article › peer-review

Abstract

SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will comprise more than 105 integrated circuits (half of which are SDRAMs and half multi-core systems-on-chip). Given this scale, it is unavoidable that some components fail and, in consequence, fault-tolerance is a foundation of the system design. Although the target application can tolerate a certain, low level of failures, important efforts have been devoted to incorporate different techniques for fault tolerance. This paper is devoted to discussing how hardware and software mechanisms collaborate to make SpiNNaker operate properly even in the very likely scenario of component failures and how it can tolerate system-degradation levels well above those expected. © 2013 The Authors. Published by Elsevier B.V. All rights reserved.

Original language	English
Pages (from-to)	693-708
Number of pages	15
Journal	Parallel Computing
Volume	39
Issue number	11
DOIs	https://doi.org/10.1016/j.parco.2013.09.001
Publication status	Published - 2013

Keywords

Fault tolerance
Globally asynchronous locally synchronous
Low power system
Massively-parallel architecture
Spiking neural networks
System-on-chip

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10.1016/j.parco.2013.09.001

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Navaridas, J., Furber, S., Garside, J., Jin, X., Khan, M., Lester, D., Luján, M., Miguel-Alonso, J., Painkras, E., Patterson, C., Plana, L. A., Rast, A., Richards, D., Shi, Y., Temple, S., Wu, J., & Yang, S. (2013). SpiNNaker: Fault tolerance in a power- and area- Constrained large-Scale neuromimetic architecture. Parallel Computing, 39(11), 693-708. https://doi.org/10.1016/j.parco.2013.09.001

@article{4ca8e9cf284748a1a0ecaa77fbe04fbb,

title = "SpiNNaker: Fault tolerance in a power- and area- Constrained large-Scale neuromimetic architecture",

abstract = "SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will comprise more than 105 integrated circuits (half of which are SDRAMs and half multi-core systems-on-chip). Given this scale, it is unavoidable that some components fail and, in consequence, fault-tolerance is a foundation of the system design. Although the target application can tolerate a certain, low level of failures, important efforts have been devoted to incorporate different techniques for fault tolerance. This paper is devoted to discussing how hardware and software mechanisms collaborate to make SpiNNaker operate properly even in the very likely scenario of component failures and how it can tolerate system-degradation levels well above those expected. {\textcopyright} 2013 The Authors. Published by Elsevier B.V. All rights reserved.",

keywords = "Fault tolerance, Globally asynchronous locally synchronous, Low power system, Massively-parallel architecture, Spiking neural networks, System-on-chip",

author = "Javier Navaridas and Steve Furber and Jim Garside and Xin Jin and Mukaram Khan and David Lester and Mikel Luj{\'a}n and Jos{\'e} Miguel-Alonso and Eustace Painkras and Cameron Patterson and Plana, {Luis A.} and Alexander Rast and Dominic Richards and Yebin Shi and Steve Temple and Jian Wu and Shufan Yang",

year = "2013",

doi = "10.1016/j.parco.2013.09.001",

language = "English",

volume = "39",

pages = "693--708",

journal = "Parallel Computing",

publisher = "Elsevier BV",

number = "11",

}

Navaridas, J, Furber, S , Garside, J, Jin, X, Khan, M, Lester, D, Luján, M, Miguel-Alonso, J, Painkras, E, Patterson, C, Plana, LA, Rast, A, Richards, D, Shi, Y, Temple, S, Wu, J & Yang, S 2013, 'SpiNNaker: Fault tolerance in a power- and area- Constrained large-Scale neuromimetic architecture', Parallel Computing, vol. 39, no. 11, pp. 693-708. https://doi.org/10.1016/j.parco.2013.09.001

TY - JOUR

T1 - SpiNNaker: Fault tolerance in a power- and area- Constrained large-Scale neuromimetic architecture

AU - Navaridas, Javier

AU - Furber, Steve

AU - Garside, Jim

AU - Jin, Xin

AU - Khan, Mukaram

AU - Lester, David

AU - Luján, Mikel

AU - Miguel-Alonso, José

AU - Painkras, Eustace

AU - Patterson, Cameron

AU - Plana, Luis A.

AU - Rast, Alexander

AU - Richards, Dominic

AU - Shi, Yebin

AU - Temple, Steve

AU - Wu, Jian

AU - Yang, Shufan

PY - 2013

Y1 - 2013

N2 - SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will comprise more than 105 integrated circuits (half of which are SDRAMs and half multi-core systems-on-chip). Given this scale, it is unavoidable that some components fail and, in consequence, fault-tolerance is a foundation of the system design. Although the target application can tolerate a certain, low level of failures, important efforts have been devoted to incorporate different techniques for fault tolerance. This paper is devoted to discussing how hardware and software mechanisms collaborate to make SpiNNaker operate properly even in the very likely scenario of component failures and how it can tolerate system-degradation levels well above those expected. © 2013 The Authors. Published by Elsevier B.V. All rights reserved.

AB - SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will comprise more than 105 integrated circuits (half of which are SDRAMs and half multi-core systems-on-chip). Given this scale, it is unavoidable that some components fail and, in consequence, fault-tolerance is a foundation of the system design. Although the target application can tolerate a certain, low level of failures, important efforts have been devoted to incorporate different techniques for fault tolerance. This paper is devoted to discussing how hardware and software mechanisms collaborate to make SpiNNaker operate properly even in the very likely scenario of component failures and how it can tolerate system-degradation levels well above those expected. © 2013 The Authors. Published by Elsevier B.V. All rights reserved.

KW - Fault tolerance

KW - Globally asynchronous locally synchronous

KW - Low power system

KW - Massively-parallel architecture

KW - Spiking neural networks

KW - System-on-chip

U2 - 10.1016/j.parco.2013.09.001

DO - 10.1016/j.parco.2013.09.001

M3 - Article

VL - 39

SP - 693

EP - 708

JO - Parallel Computing

JF - Parallel Computing

IS - 11

ER -

SpiNNaker: Fault tolerance in a power- and area- Constrained large-Scale neuromimetic architecture

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Keywords

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