TY - JOUR
T1 - SpiNNaker - programming model
AU - Brown, A.D.
AU - Furber, S.
AU - Reeve, J.S.
AU - Garside, J.D.
AU - Dugan, K.J.
AU - Plana, Luis A.
AU - Temple, Steve
N1 - This work is supported by the UK Engineering and Physical Sciences Research Council (under EPSRC grants EP/G015740/1 and EP/G015775/1), with industry partner ARM Ltd.
PY - 2014/6/13
Y1 - 2014/6/13
N2 - SpiNNaker is a multi-core computing engine, with a bespoke and specialised communication infrastructure that supports almost perfect scalability up to a hard limit of 216x18=1179648 cores. This remarkable property is achieved at the cost of ignoring memory coherency, global synchronisation and even deterministic message passing, yet it is still possible to perform meaningful computations. Whilst we have yet to assemble the full machine, the scalability properties make it possible to demonstrate the capabilities of the machine whilst it is being assembled; the more cores we connect, the larger the problems become that we are able to attack. Even with isolated printed circuit boards of 864 cores, interesting capabilities are emerging. This paper is the third of a series charting the development trajectory of the system. In the first two, we outlined the hardware build. Here, we lay out the (rather unusual) low-level foundation software developed so far to support the operation of the machine.
AB - SpiNNaker is a multi-core computing engine, with a bespoke and specialised communication infrastructure that supports almost perfect scalability up to a hard limit of 216x18=1179648 cores. This remarkable property is achieved at the cost of ignoring memory coherency, global synchronisation and even deterministic message passing, yet it is still possible to perform meaningful computations. Whilst we have yet to assemble the full machine, the scalability properties make it possible to demonstrate the capabilities of the machine whilst it is being assembled; the more cores we connect, the larger the problems become that we are able to attack. Even with isolated printed circuit boards of 864 cores, interesting capabilities are emerging. This paper is the third of a series charting the development trajectory of the system. In the first two, we outlined the hardware build. Here, we lay out the (rather unusual) low-level foundation software developed so far to support the operation of the machine.
U2 - 10.1109/TC.2014.2329686
DO - 10.1109/TC.2014.2329686
M3 - Article
SN - 0018-9340
VL - 64
SP - 1769
EP - 1782
JO - I E E E Transactions on Computers
JF - I E E E Transactions on Computers
IS - 6
ER -