STA Compatible Backend Design Flow for TSV-based 3-D ICs

Charalampos Kalargaris, Yi-Chung Chen, Vasileios Pavlidis

Research output: Contribution to conferencePosterpeer-review

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In the era of post-device scaling, three-dimensional
(3-D) integration is a promising solution to meet performance,
power, and cost requirements in modern applications, such as
IoT, high performance computing, and cyber-physical systems.
A novel design automation flow, compatible with static timing
analysis (STA), for exploring the timing and power of 3-D ICs
is proposed. Among the different types of vertical interconnects,
TSVs modeled as RC wires, are considered in this work. The
flow enables design space exploration and optimization utilizing
existing timing and power analysis tools, e.g. PrimeTime and
PrimeTimePX. The design experience is similar to a 2-D design
flow where the placement in multiple tiers is merely performed
by an open-source 3-D placer. Application of the flow to different
benchmark circuits shows that even with no optimization effort,
a two tier 3-D stack produced by the flow achieves up to 14.6%
average power reduction, 18.7% performance improvement, and
49% footprint reduction as compared to the 2-D design for a
specific circuit.
Original languageEnglish
Number of pages6
Publication statusAccepted/In press - 5 Dec 2017
EventInternational Conference on Quality Electronic Design - Santa Clara Convention Center, Santa Clara, United States
Duration: 13 Mar 201715 Mar 2017


ConferenceInternational Conference on Quality Electronic Design
Abbreviated titleISQED
Country/TerritoryUnited States
CitySanta Clara
Internet address


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