Stability Analysis of Grid-connected VSC-HVDC Systems with Compensated dq Domain Time Delay Models

Voltage Source Converters-based High Voltage Direct Current (VSC-HVDC) transmission systems using Synchronous Reference Frame-Phase-Locked Loops (SRF-PLLs) have been widely studied for modern power systems. The PLL inevitably exhibits a lag in tracking phase angle variation of the power grid voltage. This lag can introduce an equivalent time delay between the controller and systems which may result in potential stability issues. There are also various time delays within converters, which can be simplified into a lumped time delay model applied to the abc domain voltage signals. However, the inaccurate transformation of the time delay model from the abc domain to the dq domain, in which control is typically undertaken, can lead to imprecise representation. An appropriate transformation and its impact on the small-signal stability of SRF- PLL-based VSC-HVDC systems are investigated in this paper. Specifically: a small-signal state-space model of the VSC-HVDC systems is established. A compensation is derived to improve the transformation accuracy of the time delay model into the dq domain. The dq domain impedance and admittance models are then obtained for analysing the stability based on the generalized Nyquist stability criterion. The analysis results from the smallsignal model are verified through non-linear time-domain simulations in PSCAD.