Synchronization and power integrity issues in 3-D ICs

Vasilis F. Pavlidis; Hu Xu; Ioannis Tsioutsios; Giovanni De Micheli

doi:10.1109/APCCAS.2010.5775082

Synchronization and power integrity issues in 3-D ICs

Vasilis F. Pavlidis, Hu Xu, Ioannis Tsioutsios, Giovanni De Micheli

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

Several challenges should be resolved for three-dimensional integration to evolve to a mainstream technology. Among these challenges, the issues of synchronization and power integrity become predominant due to the multiple planes and the heterogeneity of 3-D circuits. The paper offers an overview of the state of the art research related to these global in nature issues. Experimental results, design techniques, and models are discussed highlighting the possible means and requirements for the design of reliable synchronization and power distribution schemes in 3-D circuits. © 2010 IEEE.

Original language	English
Title of host publication	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS\|IEEE Aisa Pac. Conf. Circuits Syst. Proc. APCCAS
Publisher	IEEE
Pages	536-539
Number of pages	3
ISBN (Print)	9781424474561
DOIs	https://doi.org/10.1109/APCCAS.2010.5775082
Publication status	Published - 2010
Event	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur Duration: 1 Jul 2010 → …

Conference

Conference	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
City	Kuala Lumpur
Period	1/07/10 → …

Keywords

3-D integration
clock distribution networks
power distribution networks
synchronization

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10.1109/APCCAS.2010.5775082

Cite this

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title = "Synchronization and power integrity issues in 3-D ICs",

abstract = "Several challenges should be resolved for three-dimensional integration to evolve to a mainstream technology. Among these challenges, the issues of synchronization and power integrity become predominant due to the multiple planes and the heterogeneity of 3-D circuits. The paper offers an overview of the state of the art research related to these global in nature issues. Experimental results, design techniques, and models are discussed highlighting the possible means and requirements for the design of reliable synchronization and power distribution schemes in 3-D circuits. {\textcopyright} 2010 IEEE.",

keywords = "3-D integration, clock distribution networks, power distribution networks, synchronization",

author = "Pavlidis, \{Vasilis F.\} and Hu Xu and Ioannis Tsioutsios and \{De Micheli\}, Giovanni",

year = "2010",

doi = "10.1109/APCCAS.2010.5775082",

language = "English",

isbn = "9781424474561",

pages = "536--539",

booktitle = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS|IEEE Aisa Pac. Conf. Circuits Syst. Proc. APCCAS",

publisher = "IEEE",

address = "United States",

note = "2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 ; Conference date: 01-07-2010",

}

Pavlidis, VF, Xu, H, Tsioutsios, I & De Micheli, G 2010, Synchronization and power integrity issues in 3-D ICs. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS|IEEE Aisa Pac. Conf. Circuits Syst. Proc. APCCAS. IEEE, pp. 536-539, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, 1/07/10. https://doi.org/10.1109/APCCAS.2010.5775082

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T1 - Synchronization and power integrity issues in 3-D ICs

AU - Pavlidis, Vasilis F.

AU - Xu, Hu

AU - Tsioutsios, Ioannis

AU - De Micheli, Giovanni

PY - 2010

Y1 - 2010

N2 - Several challenges should be resolved for three-dimensional integration to evolve to a mainstream technology. Among these challenges, the issues of synchronization and power integrity become predominant due to the multiple planes and the heterogeneity of 3-D circuits. The paper offers an overview of the state of the art research related to these global in nature issues. Experimental results, design techniques, and models are discussed highlighting the possible means and requirements for the design of reliable synchronization and power distribution schemes in 3-D circuits. © 2010 IEEE.

AB - Several challenges should be resolved for three-dimensional integration to evolve to a mainstream technology. Among these challenges, the issues of synchronization and power integrity become predominant due to the multiple planes and the heterogeneity of 3-D circuits. The paper offers an overview of the state of the art research related to these global in nature issues. Experimental results, design techniques, and models are discussed highlighting the possible means and requirements for the design of reliable synchronization and power distribution schemes in 3-D circuits. © 2010 IEEE.

KW - 3-D integration

KW - clock distribution networks

KW - power distribution networks

KW - synchronization

UR - https://www.scopus.com/pages/publications/79959236395

U2 - 10.1109/APCCAS.2010.5775082

DO - 10.1109/APCCAS.2010.5775082

M3 - Conference contribution

SN - 9781424474561

SP - 536

EP - 539

BT - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS|IEEE Aisa Pac. Conf. Circuits Syst. Proc. APCCAS

PB - IEEE

T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010

Y2 - 1 July 2010

ER -

Synchronization and power integrity issues in 3-D ICs

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Keywords

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