Abstract
Consider 4 core platform-running 4 concurrent benchmarks (instead of 2)▪ Also at 4 times the frequency of the PBX-A9▪ b/w showing good 4 cores scalability▪ Increased effective memory bandwidth for higher parallel load▪ L1 Cache bandwidths–becomes 4 times▪ DDR2 Memory bandwidth–is only showing a doubling….▪ On single instance WR benefits more from OO, write-buffer, outstanding transactions
Original language | English |
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Publisher | ARM Ltd |
Publication status | Published - 2009 |