Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators

Prachi Shukla; Sean Nemtzow; Vasilis Pavlidis; Emre Salman; Ayse Coskun

Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators

Prachi Shukla, Sean Nemtzow, Vasilis Pavlidis, Emre Salman, Ayse Coskun

Advanced Processor Technology

Research output: Contribution to conference › Paper › peer-review

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Abstract

We propose a design automation methodology to help design of energy-efficient Mono3D DNN accelerators with safe on-chip temperature for mobile systems. We introduce an optimizer capable of investigating the impact of different aspect ratios of the chip and chip footprint specifications, and selecting energy-efficient accelerators under user-specified thermal and performance constraints. We also demonstrate that using our optimizer we can reduce energy consumption by 1.6× and area by 2× with a maximum of 9.5% increase in latency compared to a Mono3D DNN accelerator optimized only for performance.

Original language	English
Publication status	Accepted/In press - 12 Sept 2020
Event	Asia South Pacific Design Automation Conference - Tokyo Odaiba Waterfront (Virtual Conference), Tokyo, Japan Duration: 18 Jan 2021 → 21 Jan 2021 http://www.aspdac.com/aspdac2021/

Conference

Conference	Asia South Pacific Design Automation Conference
Country/Territory	Japan
City	Tokyo
Period	18/01/21 → 21/01/21
Internet address	http://www.aspdac.com/aspdac2021/

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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ASP-DAC2021-1319-3Accepted author manuscript, 2.83 MBLicence: Other

Cite this

@conference{207c0b1cf291411c84b3ba4e33dce2c2,

title = "Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators",

abstract = "We propose a design automation methodology to help design of energy-efficient Mono3D DNN accelerators with safe on-chip temperature for mobile systems. We introduce an optimizer capable of investigating the impact of different aspect ratios of the chip and chip footprint specifications, and selecting energy-efficient accelerators under user-specified thermal and performance constraints. We also demonstrate that using our optimizer we can reduce energy consumption by 1.6× and area by 2× with a maximum of 9.5% increase in latency compared to a Mono3D DNN accelerator optimized only for performance.",

author = "Prachi Shukla and Sean Nemtzow and Vasilis Pavlidis and Emre Salman and Ayse Coskun",

year = "2020",

month = sep,

day = "12",

language = "English",

note = "Asia South Pacific Design Automation Conference ; Conference date: 18-01-2021 Through 21-01-2021",

url = "http://www.aspdac.com/aspdac2021/",

}

TY - CONF

T1 - Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators

AU - Shukla, Prachi

AU - Nemtzow, Sean

AU - Pavlidis, Vasilis

AU - Salman, Emre

AU - Coskun, Ayse

PY - 2020/9/12

Y1 - 2020/9/12

N2 - We propose a design automation methodology to help design of energy-efficient Mono3D DNN accelerators with safe on-chip temperature for mobile systems. We introduce an optimizer capable of investigating the impact of different aspect ratios of the chip and chip footprint specifications, and selecting energy-efficient accelerators under user-specified thermal and performance constraints. We also demonstrate that using our optimizer we can reduce energy consumption by 1.6× and area by 2× with a maximum of 9.5% increase in latency compared to a Mono3D DNN accelerator optimized only for performance.

AB - We propose a design automation methodology to help design of energy-efficient Mono3D DNN accelerators with safe on-chip temperature for mobile systems. We introduce an optimizer capable of investigating the impact of different aspect ratios of the chip and chip footprint specifications, and selecting energy-efficient accelerators under user-specified thermal and performance constraints. We also demonstrate that using our optimizer we can reduce energy consumption by 1.6× and area by 2× with a maximum of 9.5% increase in latency compared to a Mono3D DNN accelerator optimized only for performance.

M3 - Paper

T2 - Asia South Pacific Design Automation Conference

Y2 - 18 January 2021 through 21 January 2021

ER -

Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators

Abstract

Conference

UN SDGs

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