The combined effect of process variations and power supply noise on clock skew and jitter

Hu Xu; Vasilis F. Pavlidis; Wayne Burleson; Giovanni De Micheli

doi:10.1109/ISQED.2012.6187512

The combined effect of process variations and power supply noise on clock skew and jitter

Hu Xu, Vasilis F. Pavlidis, Wayne Burleson, Giovanni De Micheli

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥ 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤ 13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated. © 2012 IEEE.

Original language	English
Title of host publication	Proceedings - International Symposium on Quality Electronic Design, ISQED\|Proc. - Int. Symp. Qual. Electron. Des., ISQED
Publisher	IEEE
Pages	320-327
Number of pages	7
ISBN (Print)	9781467310369
DOIs	https://doi.org/10.1109/ISQED.2012.6187512
Publication status	Published - 2012
Event	13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA Duration: 1 Jul 2012 → …

Conference

Conference	13th International Symposium on Quality Electronic Design, ISQED 2012
City	Santa Clara, CA
Period	1/07/12 → …

Keywords

Clock distribution network
clock jitter
clock skew
power supply noise
process variations
skitter

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10.1109/ISQED.2012.6187512

Cite this

@inproceedings{ba3216de2ba648c49fd0842ab41e281c,

title = "The combined effect of process variations and power supply noise on clock skew and jitter",

abstract = "In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥ 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤ 13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated. {\textcopyright} 2012 IEEE.",

keywords = "Clock distribution network, clock jitter, clock skew, power supply noise, process variations, skitter",

author = "Hu Xu and Pavlidis, {Vasilis F.} and Wayne Burleson and {De Micheli}, Giovanni",

year = "2012",

doi = "10.1109/ISQED.2012.6187512",

language = "English",

isbn = "9781467310369",

pages = "320--327",

booktitle = "Proceedings - International Symposium on Quality Electronic Design, ISQED|Proc. - Int. Symp. Qual. Electron. Des., ISQED",

publisher = "IEEE",

address = "United States",

note = "13th International Symposium on Quality Electronic Design, ISQED 2012 ; Conference date: 01-07-2012",

}

Xu, H, Pavlidis, VF, Burleson, W & De Micheli, G 2012, The combined effect of process variations and power supply noise on clock skew and jitter. in Proceedings - International Symposium on Quality Electronic Design, ISQED|Proc. - Int. Symp. Qual. Electron. Des., ISQED. IEEE, pp. 320-327, 13th International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, 1/07/12. https://doi.org/10.1109/ISQED.2012.6187512

The combined effect of process variations and power supply noise on clock skew and jitter. / Xu, Hu; Pavlidis, Vasilis F.; Burleson, Wayne et al.
Proceedings - International Symposium on Quality Electronic Design, ISQED|Proc. - Int. Symp. Qual. Electron. Des., ISQED. IEEE, 2012. p. 320-327.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - The combined effect of process variations and power supply noise on clock skew and jitter

AU - Xu, Hu

AU - Pavlidis, Vasilis F.

AU - Burleson, Wayne

AU - De Micheli, Giovanni

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Y1 - 2012

N2 - In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥ 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤ 13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated. © 2012 IEEE.

AB - In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥ 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤ 13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated. © 2012 IEEE.

KW - Clock distribution network

KW - clock jitter

KW - clock skew

KW - power supply noise

KW - process variations

KW - skitter

U2 - 10.1109/ISQED.2012.6187512

DO - 10.1109/ISQED.2012.6187512

M3 - Conference contribution

SN - 9781467310369

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BT - Proceedings - International Symposium on Quality Electronic Design, ISQED|Proc. - Int. Symp. Qual. Electron. Des., ISQED

PB - IEEE

T2 - 13th International Symposium on Quality Electronic Design, ISQED 2012

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ER -

The combined effect of process variations and power supply noise on clock skew and jitter

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Keywords

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