The design of a dataflow coprocessor for low power embedded hierarchical processing

Power consumption has become one of the most important concerns in the design of embedded processor; the power dissipation of microprocessors grows rapidly as the development of CMOS technology packs more transistors per unit area. However, the potential for further power saving in microprocessors with a conventional architecture is limited because of their unified architectures and mature low-power techniques. An alternative approach to save power is proposed in this paper - embedding a dataflow coprocessor in a conventional RISC processor. The dataflow coprocessor is designed to execute short code segments, such as small loops, function calls and long equation evaluations, very efficiently. We demonstrate a factor of 7 improvement in power-efficiency over current general-purpose processors. Dataflow techniques are not new, but we apply the concept to address a new problem - to improve the power-efficiency of conventional processors. © Springer-Verlag Berlin Heidelberg 2006.