The Design of a Low Power Asynchronous Multiplier

Yijun Liu; Stephen Furber

doi:10.1109/LPE.2004.241065

The Design of a Low Power Asynchronous Multiplier

Yijun Liu, Stephen Furber

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low power multipliers: most inputs are positive, and most inputs have a small number of significant bits. These characteristics are exploited in the design of a multiplier that employs three techniques to minimize power consumption: asynchronous control, a radix-2 algorithm, and split registers. The power savings resulting from the use of these techniques are 55%, 23% and 12% respectively when compared to a synchronous multiplier using a radix-4 modified Booth's algorithm with unified registers. The results are derived from HSPICE simulations using input vectors from benchmark programs. A high-level software model is also used to compare the numbers of transitions in the various models.

Original language	English
Title of host publication	Proceedings of the International Symposium on Low Power Electronics and Design
Publisher	IEEE
Pages	301-306
Number of pages	6
Volume	2004-January
Edition	January
DOIs	https://doi.org/10.1109/LPE.2004.241065
Publication status	Published - 2004
Event	2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States Duration: 9 Aug 2004 → 11 Aug 2004

Conference

Conference	2004 International Symposium on Low Power Electronics and Design, ISLPED 2004
Country/Territory	United States
City	Newport Beach
Period	9/08/04 → 11/08/04

Keywords

Asynchronous logic
benchmark
Booth's algorithm
low power
multiplier

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10.1109/LPE.2004.241065

Cite this

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title = "The Design of a Low Power Asynchronous Multiplier",

abstract = "In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low power multipliers: most inputs are positive, and most inputs have a small number of significant bits. These characteristics are exploited in the design of a multiplier that employs three techniques to minimize power consumption: asynchronous control, a radix-2 algorithm, and split registers. The power savings resulting from the use of these techniques are 55%, 23% and 12% respectively when compared to a synchronous multiplier using a radix-4 modified Booth's algorithm with unified registers. The results are derived from HSPICE simulations using input vectors from benchmark programs. A high-level software model is also used to compare the numbers of transitions in the various models.",

keywords = "Asynchronous logic, benchmark, Booth's algorithm, low power, multiplier",

author = "Yijun Liu and Stephen Furber",

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language = "English",

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Liu, Y & Furber, S 2004, The Design of a Low Power Asynchronous Multiplier. in Proceedings of the International Symposium on Low Power Electronics and Design. January edn, vol. 2004-January, 1349355, IEEE, pp. 301-306, 2004 International Symposium on Low Power Electronics and Design, ISLPED 2004, Newport Beach, United States, 9/08/04. https://doi.org/10.1109/LPE.2004.241065

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N2 - In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low power multipliers: most inputs are positive, and most inputs have a small number of significant bits. These characteristics are exploited in the design of a multiplier that employs three techniques to minimize power consumption: asynchronous control, a radix-2 algorithm, and split registers. The power savings resulting from the use of these techniques are 55%, 23% and 12% respectively when compared to a synchronous multiplier using a radix-4 modified Booth's algorithm with unified registers. The results are derived from HSPICE simulations using input vectors from benchmark programs. A high-level software model is also used to compare the numbers of transitions in the various models.

AB - In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low power multipliers: most inputs are positive, and most inputs have a small number of significant bits. These characteristics are exploited in the design of a multiplier that employs three techniques to minimize power consumption: asynchronous control, a radix-2 algorithm, and split registers. The power savings resulting from the use of these techniques are 55%, 23% and 12% respectively when compared to a synchronous multiplier using a radix-4 modified Booth's algorithm with unified registers. The results are derived from HSPICE simulations using input vectors from benchmark programs. A high-level software model is also used to compare the numbers of transitions in the various models.

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KW - benchmark

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The Design of a Low Power Asynchronous Multiplier

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Keywords

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