The design of an asynchronous VHDL synthesizer

Sun Yen Tan; Stephen B. Furber; Wen Fang Yen

doi:10.1109/DATE.1998.655835

The design of an asynchronous VHDL synthesizer

Sun Yen Tan, Stephen B. Furber, Wen Fang Yen

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution

Abstract

This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on 'micropipelines', a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit. © 1998 IEEE.

Original language	English
Title of host publication	Proceedings -Design, Automation and Test in Europe, DATE\|Proc. Des. Autom. Test Eur. DATE
Publisher	IEEE Computer Society
Pages	44-51
Number of pages	7
DOIs	https://doi.org/10.1109/DATE.1998.655835
Publication status	Published - 1998
Event	Design, Automation and Test in Europe, DATE 1998 - Paris Duration: 1 Jul 1998 → … http://dblp.uni-trier.de/db/conf/date/date1998.html#TanFY98http://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98

Conference

Conference	Design, Automation and Test in Europe, DATE 1998
City	Paris
Period	1/07/98 → …
Internet address	http://dblp.uni-trier.de/db/conf/date/date1998.html#TanFY98http://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98

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10.1109/DATE.1998.655835

Cite this

@inproceedings{c10e779a2324421b891cad15d584bf6f,

title = "The design of an asynchronous VHDL synthesizer",

abstract = "This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on 'micropipelines', a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit. {\textcopyright} 1998 IEEE.",

author = "Tan, {Sun Yen} and Furber, {Stephen B.} and Yen, {Wen Fang}",

year = "1998",

doi = "10.1109/DATE.1998.655835",

language = "English",

pages = "44--51",

booktitle = "Proceedings -Design, Automation and Test in Europe, DATE|Proc. Des. Autom. Test Eur. DATE",

publisher = "IEEE Computer Society ",

address = "United States",

note = "Design, Automation and Test in Europe, DATE 1998 ; Conference date: 01-07-1998",

url = "http://dblp.uni-trier.de/db/conf/date/date1998.html#TanFY98http://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98",

}

TY - GEN

T1 - The design of an asynchronous VHDL synthesizer

AU - Tan, Sun Yen

AU - Furber, Stephen B.

AU - Yen, Wen Fang

PY - 1998

Y1 - 1998

N2 - This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on 'micropipelines', a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit. © 1998 IEEE.

AB - This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on 'micropipelines', a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit. © 1998 IEEE.

U2 - 10.1109/DATE.1998.655835

DO - 10.1109/DATE.1998.655835

M3 - Conference contribution

SP - 44

EP - 51

BT - Proceedings -Design, Automation and Test in Europe, DATE|Proc. Des. Autom. Test Eur. DATE

PB - IEEE Computer Society

T2 - Design, Automation and Test in Europe, DATE 1998

Y2 - 1 July 1998

ER -

The design of an asynchronous VHDL synthesizer

Abstract

Conference

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