The Next Generation of Exascale-Class Systems: The ExaNeSt Project

Roberto Ammendola; Andrea Biagioni; Paolo Cretaro; Ottorino Frezza; Francesca Lo Cicero; Alessandro Lonardo; Michele Martinelli; Pier Stanislao Paolucci; Elena Pastorelli; Francesco Simula; Piero Vicini; Giuliano Taffoni; Jose A. Pascual; Javier Navaridas; Mikel Luján; John Goodacree; Nikolaos Chrysos; Manolis Katevenis

doi:10.1109/DSD.2017.20

The Next Generation of Exascale-Class Systems: The ExaNeSt Project

Roberto Ammendola, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Piero Vicini, Giuliano Taffoni, Jose A. Pascual, Javier Navaridas, Mikel Luján, John Goodacree, Nikolaos Chrysos, Manolis Katevenis

Advanced Processor Technology

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

Abstract

The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an Euro-pean Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.

Original language	English
Title of host publication	Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017
Editors	Martin Novotny, Hana Kubatova, Amund Skavhaug
Publisher	IEEE
Pages	510-515
Number of pages	6
ISBN (Electronic)	9781538621455
DOIs	https://doi.org/10.1109/DSD.2017.20
Publication status	Published - 25 Sept 2017
Event	20th Euromicro Conference on Digital System Design, DSD 2017 - Vienna, Austria Duration: 30 Aug 2017 → 1 Sept 2017

Conference

Conference	20th Euromicro Conference on Digital System Design, DSD 2017
Country/Territory	Austria
City	Vienna
Period	30/08/17 → 1/09/17

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10.1109/DSD.2017.20

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Ammendola, R., Biagioni, A., Cretaro, P., Frezza, O., Lo Cicero, F., Lonardo, A., Martinelli, M., Paolucci, P. S., Pastorelli, E., Simula, F., Vicini, P., Taffoni, G., Pascual, J. A., Navaridas, J., Luján, M., Goodacree, J., Chrysos, N., & Katevenis, M. (2017). The Next Generation of Exascale-Class Systems: The ExaNeSt Project. In M. Novotny, H. Kubatova, & A. Skavhaug (Eds.), Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017 (pp. 510-515). Article 8049832 IEEE. https://doi.org/10.1109/DSD.2017.20

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title = "The Next Generation of Exascale-Class Systems: The ExaNeSt Project",

abstract = "The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an Euro-pean Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.",

author = "Roberto Ammendola and Andrea Biagioni and Paolo Cretaro and Ottorino Frezza and {Lo Cicero}, Francesca and Alessandro Lonardo and Michele Martinelli and Paolucci, {Pier Stanislao} and Elena Pastorelli and Francesco Simula and Piero Vicini and Giuliano Taffoni and Pascual, {Jose A.} and Javier Navaridas and Mikel Luj{\'a}n and John Goodacree and Nikolaos Chrysos and Manolis Katevenis",

year = "2017",

month = sep,

day = "25",

doi = "10.1109/DSD.2017.20",

language = "English",

pages = "510--515",

editor = "Martin Novotny and Hana Kubatova and Amund Skavhaug",

booktitle = "Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017",

publisher = "IEEE",

address = "United States",

note = "20th Euromicro Conference on Digital System Design, DSD 2017 ; Conference date: 30-08-2017 Through 01-09-2017",

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Ammendola, R, Biagioni, A, Cretaro, P, Frezza, O, Lo Cicero, F, Lonardo, A, Martinelli, M, Paolucci, PS, Pastorelli, E, Simula, F, Vicini, P, Taffoni, G, Pascual, JA, Navaridas, J, Luján, M, Goodacree, J, Chrysos, N & Katevenis, M 2017, The Next Generation of Exascale-Class Systems: The ExaNeSt Project. in M Novotny, H Kubatova & A Skavhaug (eds), Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017., 8049832, IEEE, pp. 510-515, 20th Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, 30/08/17. https://doi.org/10.1109/DSD.2017.20

The Next Generation of Exascale-Class Systems: The ExaNeSt Project. / Ammendola, Roberto; Biagioni, Andrea; Cretaro, Paolo et al.
Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017. ed. / Martin Novotny; Hana Kubatova; Amund Skavhaug. IEEE, 2017. p. 510-515 8049832.

Research output: Chapter in Book/Conference proceeding › Conference contribution › peer-review

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AU - Ammendola, Roberto

AU - Biagioni, Andrea

AU - Cretaro, Paolo

AU - Frezza, Ottorino

AU - Lo Cicero, Francesca

AU - Lonardo, Alessandro

AU - Martinelli, Michele

AU - Paolucci, Pier Stanislao

AU - Pastorelli, Elena

AU - Simula, Francesco

AU - Vicini, Piero

AU - Taffoni, Giuliano

AU - Pascual, Jose A.

AU - Navaridas, Javier

AU - Luján, Mikel

AU - Goodacree, John

AU - Chrysos, Nikolaos

AU - Katevenis, Manolis

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AB - The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an Euro-pean Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.

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BT - Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017

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A2 - Kubatova, Hana

A2 - Skavhaug, Amund

PB - IEEE

Y2 - 30 August 2017 through 1 September 2017

ER -

The Next Generation of Exascale-Class Systems: The ExaNeSt Project

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