Timing uncertainty in 3-D clock trees due to process variations and power supply noise

Hu Xu, Vasilis F. Pavlidis, Xifan Tang, Wayne Burleson, Giovanni De Micheli

    Research output: Contribution to journalArticlepeer-review


    Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter, for 3-D clock trees is introduced. The effect of skitter on both the setup and hold time slacks is modeled. The variation of skitter is shown to be underestimated up to 36% if process variations and dynamic power supply noise are considered separately, which highlights the importance of this unified treatment. Potential scenarios of supply noise in 3-D integrated circuits (ICs) are investigated. 3-D circuits generated from industrial benchmarks are simulated to show the skitter under these scenarios. The mean and standard deviation of skitter can vary up to 60% and 51%, respectively, due to the different amplitudes and phases of supply noise. The tradeoff between skitter and the power consumed by clock trees is also shown. A set of guidelines are presented to decrease skitter in 3-D ICs. By applying these guidelines to industrial benchmarks, simulations show a decrease in the mean skitter up to 31%. © 2013 IEEE.
    Original languageEnglish
    Article number6410052
    Pages (from-to)2226-2239
    Number of pages13
    JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
    Issue number12
    Publication statusPublished - 2013


    • 3-D ICs
    • clock jitter
    • clock skew
    • clock tree
    • power supply noise
    • process variations
    • skitter


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