Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems

Przemyslaw Mroszczyk, Vasileios Pavlidis

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

191 Downloads (Pure)


This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down to 120 mV with single ended signaling. The compensation method has negligible impact on the circuit performance and silicon area, not typically achievable by device geometry scaling. The proof-of-concept transceiver is implemented in a 65 nm CMOS technology and exhibits up to 4× higher energy efficiency at 1 Gb/s speed for 2.5 mm long chip-to-chip interconnect, as compared to state-of-the-art full swing communication schemes operating under the same conditions. The transceiver is suitable for parallel interfaces in 2.5-D integrated systems.
Original languageEnglish
Title of host publication2018 19th International Symposium on Quality Electronic Design, ISQED 2018
Number of pages6
ISBN (Electronic)9781538612149
Publication statusPublished - 2018

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295


  • 2.5-D integration
  • I/O design
  • Low swing
  • digital trimming
  • mismatch cancellation
  • passive interposer


Dive into the research topics of 'Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems'. Together they form a unique fingerprint.

Cite this