Virtual synaptic interconnect using an asynchronous network-on-chip

Alexander D. Rast, Shufan Yang, Mukaram Khan, Steve B. Furber

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Given the limited current understanding of the neural model of computation, hardware neural network architectures that impose a specific relationship between physical connectivity and model topology are likely to be overly restrictive. Here we introduce, in the SpiNNaker chip, an alternative approach: a mappable virtual topology using an asynchronous network-on-chip (NoC) that decouples the "logical" connectivity map from the physical wiring. Borrowing the established digital RAM model for synapses, we develop a concurrent memory access channel optimised for neural processing that allows each processing node to perform its own synaptic updates as if the synapses were local to the node. The highly concurrent nature of interconnect access, however, requires careful design of intermediate buffering and arbitration. We show here how a locally buffered, one-transaction-per-node model with multiple synapse updates per transaction enables the local node to offload continuous burst traffic from the NoC, allowing for a hardware-efficient design that supports biologically realistic speeds. The design not only presents a flexible model for neural connectivity but also suggests an ideal form for general-purpose high-performance on-chip interconnect. © 2008 IEEE.
Original languageEnglish
Title of host publicationProceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks
Number of pages7
ISBN (Print)9781424418213
Publication statusPublished - 2008
Event2008 International Joint Conference on Neural Networks, IJCNN 2008 - Hong Kong
Duration: 1 Jul 2008 → …


Conference2008 International Joint Conference on Neural Networks, IJCNN 2008
CityHong Kong
Period1/07/08 → …
Internet address


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