Abstract
A processor (20) is provided with a first memory protection unit (38) applying a first set of permissions and a second memory protection unit (40) applying a second set of permissions. A memory access will only be permitted if both the first set of permissions and the second set of permissions are satisfied. The processor also includes a memory management unit (42) which serves to translate from virtual addresses VA to physical addresses PA. A selectable one of the first memory protection unit (38) and the memory management unit (42) is active at any given time under control of a selection bit set by a hypervisor program (2) executing at an exception level with higher privilege than the exception level at which the guest operating systems execute
| Original language | English |
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| Patent number | US20150347052 A1 |
| Priority date | 5/02/13 |
| Publication status | Published - 3 Dec 2015 |