Vision chip with high accuracy analog S2I cells

SJ Carey, P Dudek

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    A mixed signal vision chip has been designed in a 0.18um 1P6M process. The chip incorporates a 256x256 array of processing elements, each element including 7 analog registers and 14 digital storage cells. By the programmable reconfiguration of these read/write storage elements, a compact and powerful processor array is enabled. Configuration options include setting up an array-wide analog diffusion network, and an asynchronous propagation network, allowing un-clocked inter-processor logic operations at 62x speed-up over synchronous equivalent operations. Analog registers degrade at ~1% of full-scale per second and show an offset error during a copy operation of 0.07% of register range.
    Original languageEnglish
    Title of host publication14th International Workshop on Cellular Nanoscale Networks and Applications, CNNA 2014
    PublisherIEEE
    DOIs
    Publication statusPublished - 2014

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