Abstract
Power grid analysis is a challenging problem for modern integrated circuits. For 3-D systems fabricated using stacked tiers with TSVs, traditional power grid analysis methods for planar (2-D) circuits do not demonstrate the same performance. An efficient IR drop analysis method for 3-D large-scale circuits, called 3-D voltage propagation method, is proposed in this paper. This method is compared with another widely used power grid analysis method, with preconditioned conjugated gradients. Simulation results demonstrate that the proposed method is more efficient for the IR drop analysis of large size 3-D power grids. Speedups between 10x to 20x over the preconditioned conjugated gradients method are shown. © 2012 EDAA.
| Original language | English |
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| Title of host publication | Proceedings -Design, Automation and Test in Europe, DATE|Proc. Des. Autom. Test Eur. DATE |
| Publisher | IEEE |
| Pages | 844-847 |
| Number of pages | 3 |
| ISBN (Print) | 9783981080186 |
| Publication status | Published - 2012 |
| Event | 15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 - Dresden Duration: 1 Jul 2012 → … |
Conference
| Conference | 15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 |
|---|---|
| City | Dresden |
| Period | 1/07/12 → … |
Keywords
- 3-D integrated circuits
- Power grid analysis
- Through-silicon vias