Abstract
Three-dimensional (3-D) integration has great potential to improve the power and performance of integrated circuits. Speed improvements
in 3-D ICs originate from the reduction of interconnect (RC) delay at the critical paths. The decrease in the power of a 3-D circuit is traditionally considered to result from the reduction of the interconnect capacitance and the number of repeaters due to the shorter wirelength. Since the power and performance of a circuit can significantly di↵er between the two (planar circuits) and three dimensions (multi-tier circuits) at the same operating voltage, this situation provides a voltage headroom to further improve the speed or the power of the 3-D stack. Voltage scaling can be utilized to improve either the performance or the power of 3-D circuits. In this work, emphasis is placed on reducing the operating voltage, as power savings from the reduction of the wirelength
are limited due to the non-negligible parasitic capacitance of the through silicon vias (TSVs) that vertically interconnect the tiers.
The operating voltage is decreased by exploiting the additional slack that results from the shorter length of the critical nets, such that the performance of the circuit does not change between the two and three dimensions. Guidelines and a timing model based on the logical e↵ort for identifying whether a circuit can benefit from this approach are o↵ered. In addition, a methodology for
applying and evaluating voltage reduction in 3-D ICs at the system level is presented. The typical approach of reducing power due to the decreased wire capacitance in 3-D ICs leads to moderate power savings for a variety of circuits (6.6% on average). Alternatively, the proposed approach results in a decrease in power of 22.3% on average as compared to the 2-D version of the circuits. In
addition, a decrease of 27% in the peak power is observed for a specific case study as compared to the 3-D circuit where voltage supply is not scaled and the same speed as in two-dimensions is maintained.
in 3-D ICs originate from the reduction of interconnect (RC) delay at the critical paths. The decrease in the power of a 3-D circuit is traditionally considered to result from the reduction of the interconnect capacitance and the number of repeaters due to the shorter wirelength. Since the power and performance of a circuit can significantly di↵er between the two (planar circuits) and three dimensions (multi-tier circuits) at the same operating voltage, this situation provides a voltage headroom to further improve the speed or the power of the 3-D stack. Voltage scaling can be utilized to improve either the performance or the power of 3-D circuits. In this work, emphasis is placed on reducing the operating voltage, as power savings from the reduction of the wirelength
are limited due to the non-negligible parasitic capacitance of the through silicon vias (TSVs) that vertically interconnect the tiers.
The operating voltage is decreased by exploiting the additional slack that results from the shorter length of the critical nets, such that the performance of the circuit does not change between the two and three dimensions. Guidelines and a timing model based on the logical e↵ort for identifying whether a circuit can benefit from this approach are o↵ered. In addition, a methodology for
applying and evaluating voltage reduction in 3-D ICs at the system level is presented. The typical approach of reducing power due to the decreased wire capacitance in 3-D ICs leads to moderate power savings for a variety of circuits (6.6% on average). Alternatively, the proposed approach results in a decrease in power of 22.3% on average as compared to the 2-D version of the circuits. In
addition, a decrease of 27% in the peak power is observed for a specific case study as compared to the 3-D circuit where voltage supply is not scaled and the same speed as in two-dimensions is maintained.
| Original language | English |
|---|---|
| Pages (from-to) | 35-44 |
| Number of pages | 10 |
| Journal | Microelectronics Journal |
| Volume | 69 |
| Early online date | 10 Oct 2017 |
| DOIs | |
| Publication status | Published - Nov 2017 |