Computational and Communication Architectures for Modular Multilevel Converter Construction

  • Jack Andrews

Student thesis: Phd


Renewable sources of electricity generation currently provide 47 % of the UK’s total installed capacity. Offshore wind accounts for 13 % of the total and is set to increase significantly over the next decade, driven by the UK Government’s target to reach net zero by the year 2050. An increasing number of offshore wind farms will use voltage source converter (VSC) high voltage direct current (HVDC) transmission schemes to transfer power to the onshore electricity grid. VSC-HVDC transmission is also being used to support the integration of renewables into future electricity grids. Given the rapid rollout of VSC-HVDC links, a thorough understanding of the technology is required. At present, much of the research into VSC-HVDC in the public domain fails to capture the complexities of real-world control hardware, leading to inaccuracies in simulation models. Limited research has been carried out into the effect of controller implementation in software upon real-world processing delays in modular multilevel converters (MMC). The research presented in this thesis addresses these shortcomings by providing a detailed analysis of the delays in the capacitor balancing control (CBC) loop of an MMC. Several sorting algorithms for use in the CBC loop have been implemented across a range of industrially representative control hardware and software platforms. The processing resource usage and execution delay have been measured to guide the algorithm selection process. A link between execution delay, choice of CBC method, and controller performance has been identified and is discussed. A simple method for incorporating this execution delay into a PSCAD/EMTDC simulation is then presented as a means of improving simulation model fidelity. A full suite of control software has been developed for a reduced-scale converter hardware prototype (CHP) MMC for future research into control loop delay and synchronisation. The implementation techniques developed are applicable to MMCs with a distributed control architecture in academia and industry.
Date of Award31 Dec 2022
Original languageEnglish
Awarding Institution
  • The University of Manchester
SupervisorPeter Green (Supervisor) & Mike Barnes (Supervisor)


  • Processing Delay
  • Sensor Delay
  • Actuator Delay
  • Synchronisation
  • Timing
  • Insertion Sort
  • Bubble Sort
  • LabVIEW Real-time
  • Sorting Algorithms
  • Communication Delay
  • LabVIEW
  • HVDC
  • MMC
  • Modular Multilevel Converter
  • High Voltage Direct Current
  • CBC
  • Cell Voltage Control
  • Capacitor Balancing Control
  • FPGA

Cite this