Dynamic Streamprocessing pipelines on FPGAs targeting database acceleration

  • Malte Vesper

Student thesis: Phd


With CPU performance scaling having decelerated significantly with the end of frequency scaling due to the power ceiling the industry has started to look into alternative accelerators again. This brought Cuda for GPU computing and moved GPUs in the portfolio for hosters. Another alternative that has become more and more popular recently are FPGAs. Currently FPGAs are mainly used as hot swappable ASICs. While this uses the flexibility of the FPGA to have the right `ASIC` for the task at hand, the 35x area overhead of FPGAs is a steep price to pay for this. We propose to use the reconfigurability of FPGAs to build pipelines on the fly. By using precompiled modules synthesis times can be avoided, yet the accelerator can be tailored to the task at hand.
Date of Award1 Aug 2019
Original languageEnglish
Awarding Institution
  • The University of Manchester
SupervisorJavier Navaridas (Supervisor) & Dirk Koch (Supervisor)


  • FPGA
  • PCIe
  • partial reconfiguration

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