Energy Efficient Encoding Methods For Chip-to-Chip Communication

Student thesis: Phd


As traditional scaling slows down, the number of cores and the amount of memory per system increase to satisfy the performance demand. This drive for more parallelism increases data movement requirements rapidly. However, as technology scales the energy dissipated in data communication scales at a much slower pace compared to computation energy. Therefore, new methods to reduce the energy of data transmission are explored in this thesis. Three different techniques that decrease the dynamic power of interconnects are discussed: low-swing signalling, 3-D and 2.5-D integration technologies that reduce the interconnect length, and signal encoding. An investigation of the energy benefits and limitations of low-swing signalling when applied to interposer technologies is provided, where different interposer materials are considered. Although the potential energy savings are high, low-swing signalling is susceptible to noise or induces high area penalty. Therefore, this thesis focuses on signal encoding, which reduces the bit transitions of the transmitted data to save power. Two encoding schemes are proposed, named Adaptive Word Reordering (AWR) and Serial Tuned Transition Encoding (STTE), for parallel and serial interfaces, respectively. AWR achieves a high decrease in transitions and a novel custom circuit implementation is provided to constrain the overhead in power. The power savings of AWR reach up to 23% for a 1 mm interposer-based interconnect without affecting the communication bandwidth. Alternatively, STTE is designed for source asynchronous serial interfaces, where the receiver recovers the clock from the incoming data. STTE regulates the number of transitions such that the clock can be reliably recovered while the communication energy is lowered. STTE provides at least 25% decrease in energy for a 1 mm interposer-based interconnect compared to scrambling, which is typically used in these interfaces. The ability to maintain clock recovery and, thus, link integrity is evaluated experimentally using both an electrical and an optical link that interconnect two FPGA devices.
Date of Award31 Dec 2022
Original languageEnglish
Awarding Institution
  • The University of Manchester
SupervisorVasileios Pavlidis (Supervisor) & Christoforos Moutafis (Supervisor)


  • signal integrity
  • low swing
  • bit transition
  • DC balance
  • voltage mode
  • driver
  • SSTL
  • clock recovery
  • energy efficiency
  • interconnect
  • PHY
  • interposer
  • communication
  • parallel
  • SerDes
  • encoding
  • low power
  • physical interface

Cite this