AbstractHigh Level Synthesis (HLS) tools enable application domain experts to implement applications and algorithms on FPGAs. The majority of present FPGA applications follows a stream processing model which is almost entirely implemented statically. Thus, most of the HLS FPGA designs do not exploit the benefits enabled by partial reconfiguration. In this thesis, we propose a generic approach for implementing and using partial reconfiguration through an HLS design flow for Maxeler platforms, directly from the Maxeler user experience through a language extension. Our flow extracts HLS generated HDL code from the Maxeler compilation process in order to implement a static FPGA infrastructure as well as run-time reconfigurable stream processing modules. As a distinct feature, our infrastructure can accommodate multiple partial modules in a pipeline daisy-chained manner, which aligns directly to Maxeler's dataflow programming paradigm. In addition, design choices are enabled through the proposed flow, through software and hardware implementations. Through this approach, application domain experts can design and integrate a dynamic system without focusing on the low-level details required by partial reconfiguration, while allowing flexibility by arbitrarily changing of mutually exclusive functions. All the above are done directly from the HLS aspect, with reduced implementation time of a minimum of 25\% and with up to 10ms configuration overhead. The benefits of the proposed flow are demonstrated by two case studies. In the first, a dynamically reconfigurable video processing pipeline, which delivers 6.4GB/s throughput, will be presented. This case study showcases the benefits of a dynamic implementation flow over a fully static flow. In addition, a case study for filtering database module acceleration is presented in a Maxeler platform.
|Date of Award||31 Dec 2021|
|Supervisor||James Garside (Supervisor) & Dirk Koch (Supervisor)|
- FPGA tools
- Partial Reconfiguration