Limitations imposed by the the end of Dennard Scaling have led to a significant in- crease in the power density of chips. This has elevated power efficiency to a first order design constraint. This thesis proposes a novel microbenchmark generator, the Generator of LLVM Assisted Microbenchmarks (GLAM), a tool which enables the generation of architec- ture agnostic microbenchmarks by exploiting the LLVM Intermediate Representation. GLAM can be used for design space exploration, as a tool to aid in power model gen- eration, and has been used to evaluate the power management scheme described in this thesis. Furthermore, a novel power management scheme, Cyclical Power Gating (CPG), is proposed. CPG exploits a state-retentive power-gating technique that allows power consumption to be scaled linearly without reducing the supply voltage. CPG works by turning the core on and off over a parameterised period and duty cycle. The low switching overhead of CPG can be used to apply it at the granularity of program func- tion level, and provides Energy Delay Product (EDP) gains when compared to nominal operation. A simulation-based comparison of CPG with equivalent voltage and frequency lev- els of a system equipped with Dynamic Voltage and Frequency Scaling shows that CPG provides 6.27% better Energy-Delay-Product than Voltage and Frequency Scaling.
|Date of Award||1 Aug 2018|
- The University of Manchester
|Supervisor||Mikel Luján (Supervisor) & Javier Navaridas (Supervisor)|