TOWARDS PROCESS CONTEXT DRIVEN AND PMU UPDATED PREEMPTIVE SCHEDULING FOR SINGLE-ISA HETEROGENEOUS SYSTEMS

Abstract

The continuous growth of computer systems have introduced a new era for computing. The performance and power gains that came through advancements in transistor technology driven by Moore’s law have begun to diminish due to the Dennard’s Scaling hitting the physical boundaries. The increasing demand for performance along with resource constraints have brought energy and power efficiency to the forefront of research agenda. Power efficiency requirement is imposed by thermal problems in modern chips while energy efficiency is needed for long lasting batteries and low electricity costs. The inability of multi-core processors to meet the above requirements have shifted research towards heterogeneous architectures. This thesis focuses on single-ISA heterogeneous architectures or asymmetric multicores, where two or more core types are integrated onto the same chip. All core types implement the same Instruction Set Architecture (ISA), but differ at the micro- architecture level and/or operating frequency, thus delivering different performance and power/energy efficiency. A major challenge in single-ISA heterogeneous architectures is scheduling. This thesis explores scheduling techniques on single-ISA heterogeneous architectures, and more specifically on ARM big.LITTLE systems. The state-of-the-art schedulers for big.LITTLE systems are based on the default Time Preemptive Scheduling mechanism of Linux kernel which can miss rapid phase changes of the workload. This thesis proposes a novel scheduling mechanism, called Context Preemptive Scheduling, that exploits features of ARM architecture to closely track phase changes in running programs and invokes the migration process of the scheduler in time. More speciffically, it leverages the fact that the ARM PMU creates an interrupt when Hardware Performance Counters-HPCs overflow. In Context Preemptive Scheduling the HPCs can be set to such values so as to overflow when the workload changes its behaviour. The overflow triggers an interrupt which in turn initiates the procedure to check if migration is needed. This approach, tested under a small set of micro-benchmarks and MiBench benchmark, manages to closely track the phase changes of the workload and can perform process migration more rapidly in cases where it is needed; thus it shows promise in delivering better run-time performance and energy efficiency compared to the default time preemptive scheduling mechanism.

Date of Award	1 Aug 2022
Original language	English
Awarding Institution	The University of Manchester
Supervisor	Mikel Luján (Supervisor) & Anthony Goodacre (Supervisor)